Digital systems design with VHDL and synthesis : an integrated approach / K.C. Chang.

By:

Chang, K. C. (Kou-Chuan), 1957-

Material type: Text

TextPublication details: Los Alamitos, Calif. : IEEE Computer Society, c1999.Description: xv, 499 p. : ill. ; 27 cmISBN:

0769500234

Subject(s):

DDC classification:

621.392 CHA

Holdings
Item type	Current library	Call number	Copy number	Status	Date due	Barcode
Standard Loan	Moylish Library Main Collection	621.392 CHA (Browse shelf(Opens below))	1	Available		39002000219767
Standard Loan	Moylish Library Main Collection	621.392 CHA (Browse shelf(Opens below))	2	Available		39002000219783

Enhanced descriptions from Syndetics:

K.C. Chang presents an integrated approach to digital design principles, processes, and implementations to help the reader design increasingly complex systems within shorter design cycles. Chang introduces digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together.

Digital Systems Design with VHDL and Synthesis focuses on the ultimate product of the design cycle: the implementation of a digital design. Many of the design techniques and considerations illustrated in the text are examples of actual real-world designs.

Unique features of the book include the following:

VHDL code explained line by line to capture the logic behind the design concepts Simulation waveforms, synthesized schematics, and results are shown, verified, and analyzed VHDL code is synthesized and commands and strategies are discussed Variations on the design techniques and common mistakes are addressed Demonstrated standard cell, gate array, and FPGA three design processes, each with a complete design case study Test bench, post-layout verification, and test vector generation processes are illustrated

Includes bibliographical references and index.

Table of contents provided by Syndetics

Chapter 1 Introduction (p. 1)
1.1 Integrated Design Process and Methodology (p. 1)
1.2 Book Overview (p. 2)
Chapter 2 VHDL and Digital Circuit Primitives (p. 4)
2.1 Flip Flop (p. 4)
2.2 Latch (p. 15)
2.3 Three-State Buffer (p. 18)
2.4 Combinational Gates (p. 22)
2.5 VHDL Synthesis Rules (p. 26)
2.6 Pads (p. 30)
2.7 Exercises (p. 30)
Chapter 3 VHDL Simulation and Synthesis Environment and Design Process (p. 32)
3.1 Synopsys VHDL Simulation Environment Overview (p. 32)
3.2 Mentor Quick VHDL Simulation Environment (p. 36)
3.3 Synthesis Environment (p. 39)
3.4 Synthesis Technology Library (p. 45)
3.5 VHDL Design Process for a Block (p. 47)
3.6 Exercises (p. 52)
Chapter 4 Basic Combinational Circuits (p. 53)
4.1 Selector (p. 53)
4.2 Encoder (p. 68)
4.3 Code Converter (p. 71)
4.4 Equality Checker (p. 73)
4.5 Comparator with Single Output (p. 79)
4.6 Comparator with Multiple Outputs (p. 82)
4.7 Exercises (p. 89)
Chapter 5 Basic Binary Arithmetic Circuits (p. 91)
5.1 Half Adder and Full Adder (p. 91)
5.2 Carry Ripple Adder (p. 97)
5.3 Carry Look Ahead Adder (p. 101)
5.4 Countone Circuit (p. 119)
5.5 Leading Zero Circuit (p. 123)
5.6 Barrel Shifter (p. 132)
5.7 Exercises (p. 137)
Chapter 6 Basic Sequential Circuits (p. 143)
6.1 Signal Manipulator (p. 143)
6.2 Counter (p. 150)
6.3 Shift Register (p. 166)
6.4 Parallel to Serial Converter (p. 177)
6.5 Serial to Parallel Converter (p. 180)
6.6 Exercises (p. 186)
Chapter 7 Registers (p. 187)
7.1 General Framework for Designing Registers (p. 187)
7.2 Interrupt Registers (p. 189)
7.3 DMA and Control Registers (p. 193)
7.4 Configuration Registers (p. 196)
7.5 Reading Registers (p. 201)
7.6 Register Block Partitioning and Synthesis (p. 202)
7.7 Testing Registers (p. 213)
7.8 Microprocessor Registers (p. 219)
7.9 Exercises (p. 221)
Chapter 8 Clock and Reset Circuits (p. 222)
8.1 Clock Buffer and Clock Tree (p. 222)
8.2 Clock Tree Generation (p. 225)
8.3 Reset Circuitry (p. 228)
8.4 Clock Skew and Fixes (p. 230)
8.5 Synchronization between Clock Domains (p. 238)
8.6 Clock Divider (p. 242)
8.7 Gated Clock (p. 246)
8.8 Exercises (p. 250)
Chapter 9 Dual-Port RAM, FIFO, and Dram Modeling (p. 251)
9.1 Dual-Port RAM (p. 251)
9.2 Synchronous FIFO (p. 260)
9.3 Asynchronous FIFO (p. 266)
9.4 Dynamic Random Access Memory (DRAM) (p. 274)
9.5 Exercises (p. 286)
Chapter 10 A Design Case Study: Finite Impulse Response Filter Asic Design (p. 288)
10.1 Design Description (p. 288)
10.2 Design Partition (p. 293)
10.3 Design Verification (p. 307)
10.4 Design Synthesis (p. 322)
10.5 Worst-Case Timing Analysis (p. 325)
10.6 Best-Case Timing Analysis (p. 329)
10.7 Netlist Generation (p. 331)
10.8 Postlayout Verification (p. 334)
10.9 Design Management (p. 337)
10.10 Exercises (p. 339)
Chapter 11 A Design Case Study: A Microprogram Controller Design (p. 341)
11.1 Microprogram Controller (p. 341)
11.2 Design Description and Partition (p. 344)
11.3 Design Verification (p. 362)
11.4 Design Synthesis (p. 377)
11.5 Postsynthesis Timing Verification (p. 382)
11.6 Preparing Release Functional Vectors (p. 383)
11.7 Postlayout Verification (p. 387)
11.8 Design Management (p. 387)
11.9 Exercises (p. 389)
Chapter 12 Error Detection and Correction (p. 390)
12.1 Error Detection and Correction Code (p. 390)
12.2 Single Error Detecting Codes (p. 390)
12.3 Single Error Correcting Codes (p. 391)
12.4 Single Error Correcting and Double Error Detecting Codes (p. 393)
12.5 Error Detecting and Correcting Code Design Example (p. 394)
12.6 Design Verification (p. 400)
12.7 Design Synthesis (p. 403)
12.8 Netlist Generation and FPGA Place and Route (p. 407)
12.9 Exercises (p. 407)
Chapter 13 Fixed-Point Multiplication (p. 408)
13.1 Multiplication Concept (p. 408)
13.2 Unsigned Binary Multiplier (p. 409)
13.3 2's Complement Multiplication (p. 419)
13.4 Wallace Tree Adders (p. 423)
13.5 Booth-Wallace Tree Multiplier (p. 425)
13.6 Booth-Wallace Tree Multiplier Verification (p. 429)
13.7 Booth-Wallace Tree Multiplier Synthesis (p. 431)
13.8 Multiplication with Shift and Add (p. 437)
13.9 Exercises (p. 442)
13.10 References (p. 444)
Chapter 14 Fixed-Point Division (p. 445)
14.1 Basic Division Concept (p. 445)
14.2 32-Bit Divider (p. 451)
14.3 Design Partition (p. 452)
14.4 Design Optimization (p. 453)
14.5 Design Verification (p. 458)
14.6 Design Synthesis (p. 462)
14.7 Exercises (p. 465)
14.8 Reference (p. 466)
Chapter 15 Floating-Point Arithmetic (p. 467)
15.1 Floating-Point Number Representation (p. 467)
15.2 Floating-Point Addition (p. 468)
15.3 Floating-Point Multiplication (p. 479)
15.4 Exercises (p. 484)
Appendix A Package Pack (p. 485)
Index (p. 496)

Author notes provided by Syndetics

Kwang-chih Chang, commonly known as K.C. Chang, was a Chinese-American archaeologist and sinologist. He was the John E. Hudson Professor of archaeology at Harvard University, Vice-President of the Academia Sinica, and a curator at the Peabody Museum of Archaeology and Ethnology.

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