Computer organization and design : the hardware / software interface / David A. Patterson, John L. Hennessy.

Enhanced descriptions from Syndetics:

Computer Organization and Design, Fifth Edition , is the latest update to the classic introduction to computer organization. The text now contains new examples and material highlighting the emergence of mobile computing and the cloud. It explores this generational change with updated content featuring tablet computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures. The book uses a MIPS processor core to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O.Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, Going Faster, used throughout the text to demonstrate extremely effective optimization techniques. There is also a new discussion of the Eight Great Ideas of computer architecture. Parallelism is examined in depth with examples and content highlighting parallel hardware and software topics. The book features the Intel Core i7, ARM Cortex-A8 and NVIDIA Fermi GPU as real-world examples, along with a full set of updated and improved exercises.This new edition is an ideal resource for professional digital system designers, programmers, application developers, and system software developers. It will also be of interest to undergraduate students in Computer Science, Computer Engineering and Electrical Engineering courses in Computer Organization, Computer Design, ranging from Sophomore required courses to Senior Electives.

Table of contents provided by Syndetics

• Preface (p. xv)
• 1 Computer Abstractions and Technology (p. 2)
• 1.1 Introduction (p. 3)
• 1.2 Eight Great Ideas in Computer Architecture (p. 11)
• 1.3 Below Your Program (p. 13)
• 1.4 Under the Covers (p. 16)
• 1.5 Technologies for Building Processors and Memory (p. 24)
• 1.6 Performance (p. 28)
• 1.7 The Power Wall (p. 40)
• 1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors (p. 43)
• 1.9 Real Stuff: Benchmarking the Intel Core i7 (p. 46)
• 1.10 Fallacies and Pitfalls (p. 49)
• 1.11 Concluding Remarks (p. 52)
• 1.12 Historical Perspective and Further Reading (p. 54)
• 1.13 Exercises (p. 54)
• 2 Instructions: Language of the Computer (p. 60)
• 2.1 Introduction (p. 62)
• 2.2 Operations of the Computer Hardware (p. 63)
• 2.3 Operands of the Computer Hardware (p. 66)
• 2.4 Signed and Unsigned Numbers (p. 73)
• 2.5 Representing Instructions in the Computer (p. 80)
• 2.6 Logical Operations (p. 87)
• 2.7 Instructions for Making Decisions (p. 90)
• 2.8 Supporting Procedures in Computer Hardware (p. 96)
• 2.9 Communicating with People (p. 106)
• 2.10 MIPS Addressing for 32-Bit Immediates and Addresses (p. 111)
• 2.11 Parallelism and Instructions: Synchronization (p. 121)
• 2.12 Translating and Starting a Program (p. 123)
• 2.13 AC Sort Example to Put It All Together (p. 132)
• 2.14 Arrays versus Pointers (p. 141)
• 2.15 Advanced Material: Compiling C and Interpreting Java (p. 145)
• 2.16 Real Stuff: ARMv7 (32-bit) Instructions (p. 145)
• 2.17 Real Stuff: x86 Instructions (p. 149)
• 2.18 Real Stuff: ARMv8 (64-bit) Instructions (p. 158)
• 2.19 Fallacies and Pitfalls (p. 159)
• 2.20 Concluding Remarks (p. 161)
• 2.21 Historical Perspective and Further Reading (p. 163)
• 2.22 Exercises (p. 164)
• 3 Arithmetic for Computers (p. 176)
• 3.1 Introduction (p. 178)
• 3.2 Addition and Subtraction (p. 178)
• 3.3 Multiplication (p. 183)
• 3.4 Division (p. 189)
• 3.5 Floating Point (p. 196)
• 3.6 Parallelism and Computer Arithmetic: Subword Parallelism (p. 222)
• 3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86 (p. 224)
• 3.8 Going Faster: Subword Parallelism and Matrix Multiply (p. 225)
• 3.9 Fallacies and Pitfalls (p. 229)
• 3.10 Concluding Remarks (p. 232)
• 3.11 Historical Perspective and Further Reading (p. 236)
• 3.12 Exercises (p. 237)
• 4 The Processor (p. 242)
• 4.1 Introduction (p. 244)
• 4.2 Logic Design Conventions (p. 248)
• 4.3 Building a Datapath (p. 251)
• 4.4 A Simple Implementation Scheme (p. 259)
• 4.5 An Overview of Pipelining (p. 272)
• 4.6 Pipelined Datapath and Control (p. 286)
• 4.7 Data Hazards: Forwarding versus Stalling (p. 303)
• 4.8 Control Hazards (p. 316)
• 4.9 Exceptions (p. 325)
• 4.10 Parallelism via Instructions (p. 332)
• 4.11 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Pipelines (p. 344)
• 4.12 Going Faster: Instruction-Level Parallelism and Matrix Multiply (p. 351)
• 4.13 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations (p. 354)
• 4.14 Fallacies and Pitfalls (p. 355)
• 4.15 Concluding Remarks (p. 356)
• 4.16 Historical Perspective and Further Reading (p. 357)
• 4.17 Exercises (p. 357)
• 5 Large and Fast: Exploiting Memory Hierarchy (p. 372)
• 5.1 Introduction (p. 374)
• 5.2 Memory Technologies (p. 378)
• 5.3 The Basics of Caches (p. 383)
• 5.4 Measuring and Improving Cache Performance (p. 398)
• 5.5 Dependable Memory Hierarchy (p. 418)
• 5.6 Virtual Machines (p. 424)
• 5.7 Virtual Memory (p. 427)
• 5.8 A Common Framework for Memory Hierarchy (p. 454)
• 5.9 Using a Finite-State Machine to Control a Simple Cache (p. 461)
• 5.10 Parallelism and Memory Hierarchies: Cache Coherence (p. 466)
• 5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks (p. 470)
• 5.12 Advanced Material: Implementing Cache Controllers (p. 470)
• 5.13 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies (p. 471)
• 5.14 Going Faster: Cache Blocking and Matrix Multiply (p. 475)
• 5.15 Fallacies and Pitfalls (p. 478)
• 5.16 Concluding Remarks (p. 482)
• 5.17 Historical Perspective and Further Reading (p. 483)
• 5.18 Exercises (p. 483)
• 6 Parallel Processors from Client to Cloud (p. 500)
• 6.1 Introduction (p. 502)
• 6.2 The Difficulty of Creating Parallel Processing Programs (p. 504)
• 6.3 SISD.MLMD, SIMD, SPMD, and Vector (p. 509)
• 6.4 Hardware Multithreading (p. 516)
• 6.5 Multicore and Other Shared Memory Multiprocessors (p. 519)
• 6.6 Introduction to Graphics Processing Units (p. 524)
• 6.7 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors (p. 531)
• 6.8 Introduction to Multiprocessor Network Topologies (p. 536)
• 6.9 Communicating to the Outside World: Cluster Networking (p. 539)
• 6.10 Multiprocessor Benchmarks and Performance Models (p. 540)
• 6.11 Real Stuff: Benchmarking Intel Core 17 versus NVIDIA Tesla GPU (p. 550)
• 6.12 Going Faster: Multiple Processors and Matrix Multiply (p. 555)
• 6.13 Fallacies and Pitfalls (p. 558)
• 6.14 Concluding Remarks (p. 560)
• 6.15 Historical Perspective and Further Reading (p. 563)
• 6.16 Exercises (p. 563)
• Appendices
• A Assemblers, Linkers, and the SPIM Simulator (p. A-2)
• A.1 Introduction (p. A-3)
• A.2 Assemblers (p. A-10)
• A.3 Linkers (p. A-18)
• A.4 Loading (p. A-19)
• A.5 Memory Usage (p. A-20)
• A.6 Procedure Call Convention (p. A-22)
• A.7 Exceptions and Interrupts (p. A-33)
• A.8 Input and Output (p. A-38)
• A.9 SPIM (p. A-40)
• A.10 MIPS R2000 Assembly Language (p. A-45)
• A.11 Concluding Remarks (p. A-81)
• A.12 Exercises (p. A-82)
• B The Basics of Logic Design (p. B-2)
• B.1 Introduction (p. B-3)
• B.2 Gates, Truth Tables, and Logic Equations (p. B-4)
• B.3 Combinational Logic (p. B-9)
• B.4 Using a Hardware Description Language (p. B-20)
• B.5 Constructing a Basic Arithmetic Logic Unit (p. B-26)
• B.6 Faster Addition: Carry Lookahead (p. B-38)
• B.7 Clocks (p. B-48)
• B.8 Memory Elements: Flip-Flops, Latches, and Registers (p. B-50)
• B.9 Memory Elements: SRAMs and DRAMs (p. B-58)
• B.10 Finite-State Machines (p. B-67)
• B.11 Timing Methodologies (p. B-72)
• B.12 Field Programmable Devices (p. B-78)
• B.13 Concluding Remarks (p. B-79)
• B.14 Exercises (p. B-80)
• Index (p. I-1)
• Graphics and Computing GPUs (p. C-2)
• C.1 Introduction (p. C-3)
• C.2 GPU System Architectures (p. C-7)
• C.3 Programming GPUs (p. C-12)
• C.4 Multithreaded Multiprocessor Architecture (p. C-25)
• C.5 Parallel Memory System (p. C-36)
• C.6 Floating Point Arithmetic (p. C-41)
• C.7 Real Stuff: The NVIDIA GeForce 8800 (p. C-46)
• C.8 Real Stuff: Mapping Applications to GPUs (p. C-55)
• C.9 Fallacies and Pitfalls (p. C-72)
• C.10 Concluding Remarks (p. C-76)
• C.11 Historical Perspective and Further Reading (p. C-77)
• Mapping Control to Hardware (p. D-2)
• D.1 Introduction (p. D-3)
• D.2 Implementing Combinational Control Units (p. D-4)
• D.3 Implementing Finite-State Machine Control (p. D-8)
• D.4 Implementing the Next-State Function with a Sequencer (p. D-22)
• D.5 Translating a Microprogram to Hardware (p. D-28)
• D.6 Concluding Remarks (p. D-32)
• D.7 Exercises (p. D-33)
• A Survey of RISC Architectures for Desktop, Server, and Embedded Computers (p. E-2)
• E.1 Introduction (p. E-3)
• E.2 Addressing Modes and Instruction Formats (p. E-5)
• E.3 Instructions: The MIPS Core Subset (p. E-9)
• E.4 Instructions: Multimedia Extensions of the Desktop/Server RISCs (p. E-16)
• E.5 Instructions: Digital Signal-Processing Extensions of the Embedded RISCs (p. E-19)
• E.6 Instructions: Common Extensions to MIPS Core (p. E-20)
• E.7 Instructions Unique to MIPS-64 (p. E-25)
• E.8 Instructions Unique to Alpha (p. E-27)
• E.9 Instructions Unique to SPARC v9 (p. E-29)
• E.10 Instructions Unique to PowerPC (p. E-32)
• E.11 instructions Unique to PA-RISC 2.0 (p. E-34)
• E.12 Instructions Unique to ARM (p. E-36)
• E.13 Instructions Unique to Thumb (p. E-38)
• E.14 Instructions Unique to SuperH (p. E-39)
• E.15 Instructions Unique to M32R (p. E-40)
• E.16 Instructions Unique to MIPS-16 (p. E-40)
• E.17 Concluding Remarks (p. E-43)
• Glossary (p. G-1)
• Further Reading (p. FR-1)

Author notes provided by Syndetics